The present invention relates to a digital communication system having an error correction circuit.
In a prior art digital radio communication system as shown in FIG. 9, an input signal is processed by a transmit code processor 40 at the transmitting end of the system to produce a data bit stream which is fed to an error correction encoder 42 where error correcting codes are added and modulated by a transmitter 43 and sent over a radio link to a receiving end of the link. At the receiving end of the link, the signal is demodulated by a receiver 46 and fed to an error correction decoder 45 to correct data bits in error and applied to a receive code processor 44 to treat it in a process inverse to that of transmit code processor 40. Details of the transmit code processor 40, error correction encoder 42, error correction decoder 45 and receiver code processor 44 are shown in FIGS. 10 and 11.
In FIG. 10, transmit code processor 40 includes a multiplexer 51 to which a main signal and an auxiliary signal are applied. A timing signal generator 52 generates a timing output pulse which causes a frame sync generator 53 to supply a frame sync code to the multiplexer 51. Input data signals are multiplexed with the frame sync code into an output data stream in response to a timing signal from generator 52 and fed to a data compression memory 54 of the error correction encoder 42. Error correction encoder 42 is provided with a timing signal generator 56 whose output determines the rate of compression of the time dimension of data. Compression memory 54 compresses the time dimension of its input signal into groups of clustered data bits to provide time slots for insertion of redundant bits. The time-compressed data bits are fed to a redundant bit generator 55 to allow it detect timing for bit insertion and generate error correction redundant bits which are inserted to the time-compressed data stream by a bit adder 57 and sent to the receiver 46 at the receiving end.
In FIG. 11, error correction decoder 45 includes a delay circuit 61 and a redundant bit decoder 62 to both of which the output of receiver 46 is applied. Decoder 62 supplies a syndrome to an error corrector 64 and a word synchronizer 65. Word synchronizer 65 supplied a hunting pulse to a timing signal generator 63 to cause it to be word synchronized. The input signal applied to delay circuit 61 is delayed until redundant bit decoding operation is complete and fed to error corrector 64. Data bits in error are corrected using the syndrome supplied from decoder 62 and fed to a data expansion memory circuit 66 where the time dimension of the data is recovered, while removing the inserted redundant bits.
The output of expansion memory circuit 66 is applied to a frame synchronizer 68 which detects the frame sync code by checking it against a frame sync code generated by a frame sync generator 70 and supplied a hunting pulse to a timing signal generator 69 to cause it to generate a timing signal to frame sync generator 70 at frame-synchronized timing. Input data from memory circuit 66 is demultiplexed into separate signals by a timing signal received from generator 69.
With the aforesaid prior art frame synchronization circuit, word synchronization is established prior to the establishment of frame synchronization. As a result, it takes longer to establish frame synchronization and requires duplication of similar sync detecting circuits.